1. Field of the Invention
The present invention relates to a semiconductor memory device using a serial pointer such as a First In First Out (FIFO) semiconductor memory device, a field memory and the like, and, in particular, to a semiconductor memory device being capable of asynchronous high speed write-in and read-out during serial input and output of data to memory elements of the semiconductor memory device using a serial pointer.
2. Description of the Prior Art
Among memories in which data is write in to and read out from a memory cell serially, such as First In First Out (FIFO) memories and field memories, a serial pointer is used to count column addresses, one address at a time, in synchronism with an external serial clock signal, to select a column.
FIG. 1 is a configuration drawing of a conventional First In First Out (FIFO) semiconductor memory device provided with a column of N bits.
FIG. 2 is a diagram for explaining the operation of a conventional serial pointer including a required number of pointers used for the conventional FIFO memory device shown in FIG. 1.
First, an operation for writing data into memory cells will be explained.
Each of data input transferred from an external device has a value of digital "1" ("H" level) or digital "0" ("L" level) in an input buffer (not shown). These data are transferred to write-data lines (not shown), and data from a column address 1 to a column address N/2 are serially received in sequence to a first write register WR1 based on the serial write pointers.
When data have been received to all the bits of the first write register WR1, a word line for selecting the row direction of a memory cell array is selected by a row decoder RD controlled by an internal circuit in the FIFO semiconductor memory device (chip), and the data in the first write register WR1 is written into a first memory cell array MCA1 through a first write transfer gate WTI.
Simultaneously, data from an address (N/2)+1 to an address N are serially transferred in sequence to a second write register WR2. When the data have been received to all the bits of the second write register WR2, the data in the second write register WR2 are written into a second memory cell array MCA2 through a second write transfer gate WT2, and the word line selection is completed.
The position of a serial write pointer (SWP) for selecting the N address register bit returns back to the position for selecting the first address register bit, and the above-mentioned operation is repeated so that the operation of writing to the memory cell is carried out.
Second, an operation for reading data from a memory cell will be explained.
A word line is selected to read out data from the memory cell array. The read-out data is sensed by a sense amplifier SA and amplified, then the data in the first memory cell array MCA1 is transferred to a first read register RR1 through a first read transfer gate RT1 and latched.
The data from the column address 1 to the column address N/2 of the first read register RR1 are then serially transferred in sequence by a serial read pointer SRP, transferred to data lines, and transmitted externally through an output buffer (not shown).
Simultaneously, the data in the second memory cell array MCA2 are transferred to a second read register RR2 through a second read transfer gate RT2 and latched, and the word line selection is completed.
When the data in all the bits of the first read register RR1 has been read out, the serial read pointer SRP reads out the data from the address (N/2) +1 to the address N in the second read register RR2.
Simultaneously, a word line is selected and data are read out from the memory cell. The read-out data are sensed by the sense amplifier SA and amplified, then the data in the first memory cell array MCA1 are transferred to the first read register RR1 through the first read transfer gate RT1 and latched. When the data have been read out of all the bits of the second read register RR2, the position of the serial read pointer SRP for selecting the N address register bit returns back to the pointer position for selecting the first address register bit and the above-mentioned operation is repeated so that the data are read from the memory cell.
In the conventional FIFO semiconductor memory device shown in FIG. 1, there is the problem that the delay caused by the length of a wiring is large when the serial pointer reverts to the position for selecting the first address register from the position for selecting the N address register bit because the length of the wiring is extremely long in comparison with the length of wiring or spacing between the other adjacent pointers, namely bit elements of the pointers.
In the configuration of the conventional FIFO semiconductor memory device shown in FIG. 1, when the above-mentioned read and write operations are carried out simultaneously, there is the problem that, for example, the word line for the write operation cannot be selected during the selection of the word line for the read operation.
Also, conversely, the word line for the read operation cannot be selected during the selection of the word line for the write operation. In recent years, the need for high speed serial access has increased, but it has not been possible to adequately cope with this requirement for high speed serial access for the above-mentioned reasons and the like.